Interra Systems has production-proven expertise in developing HDL Front-Ends. Interra markets analyzers for Verilog, SystemVerilog, VHDL, UPF, CPF, Spice and several other EDA standards. Latest standard compliant and easy to use building blocks from Interra Systems enable users to reduce time-to-market by saving a significant amount of development time. Interra’s customers include top-tier EDA vendors, EDA startup companies and internal CAD groups of SoC companies. EDA Tools that integrate Interra’s EDA Objects are in production-use on thousands of chip designs. Interra ensures its front-ends keep pace with language enhancements, capacity and quality requirements.
Cheetah is a full language Verilog and SystemVerilog Front-End Analyzer. It fully supports following standards:
Cheetah parses all versions of standards of SystemVerilog and Verilog and creates an in-memory Object Model. Applications can then access the design information instantly using efficient generic programming interface. Standard compliant and easy to use building blocks from Interra Systems enable users to reduce time-to-market by saving a significant amount of development time.
Front-end analyzers from Interra Systems are widely used by top-tier EDA tool developers as a universal front-end to their design solutions. Interra’s customers include top-tier EDA vendors, EDA startup companies and internal CAD groups of SoC companies. EDA Tools that integrate Interra’s EDA Objects are in production-use on thousands of chip designs.
Interra ensures its front-ends keep pace with language enhancements, capacity and quality requirements.
Key FeaturesJaguar is a full language VHDL Front-End Analyzer. It fully supports following standards:
Jaguar parses all versions of standards of VHDL and creates an in-memory Object Model. Applications can then access the design information instantly using efficient generic programming interface. Standard compliant and easy to use building blocks from Interra Systems enable users to reduce time-to-market by saving a significant amount of development time.
Front-end analyzers from Interra Systems are widely used by top-tier EDA tool developers as a universal front-end to their design solutions. Interra’s customers include top-tier EDA vendors, EDA startup companies and internal CAD groups of SoC companies. EDA Tools that integrate Interra’s EDA Objects are in production-use on thousands of chip designs.
Interra ensures its front-ends keep pace with language enhancements, capacity and quality requirements.
Key FeaturesMost of the complex SoC designs today use one or more of Verilog, SystemVerilog and VHDL to implement various sub-systems. EDA tool developer needs to provide support for mixed language parsing.
MixedHDL from Interra Systems uses Cheetah, the Verilog and SystemVerilog front-end analyzer and Jaguar, the VHDL front-end analyzer to bring MixedHDL capability for EDA tool developers. Programming layer of MixedHDL analyzes mixed designs and elaborates cross-HDL instances. EDA tool developers can bring mixed-language support to their tool quickly. Language specific functionality is available through Cheetah and Jaguar API layer.
MixedHDL supports following EDA standards:
MixedHDL in conjunction with Cheetah and Jaguar parses all versions of standards of Verilog, SystemVerilog and VHDL and creates an in-memory Object Model. Applications can then access the design information instantly using efficient generic programming interface. Standard compliant and easy to use building blocks from Interra Systems enable users to reduce time-to-market by saving a significant amount of development time.
Front-end analyzers from Interra Systems are widely used by top-tier EDA tool developers as a universal front-end to their design solutions. Interra’s customers include top-tier EDA vendors, EDA startup companies and internal CAD groups of SoC companies. EDA Tools that integrate Interra’s EDA Objects are in production-use on thousands of chip designs.
Interra ensures its front-ends keep pace with language enhancements, capacity and quality requirements.
Key FeaturesNOM is a language-independent front-end for Netlist applications. It analyzes Verilog, VHDL and EDIF netlists and creates a language neutral Object Model for connectivity. Applications can then access the design information in the Object Model using common Programming Interface, thus saving enormous time and resources. Rather than spending time writing parsers and multiple front-ends for different language inputs, designers can now spend time designing their solutions.
Extensive customization capabilities allow EDA tool developers to extend and mould NOM as per their needs. NOM is used as the front-end for a diverse set of EDA applications to increase the speed of development.
Key FeaturesConcorde creates structural implementation for given Register Transfer Level hardware description in System Verilog, Verilog, VHDL, and mixed languages. This language neutral solution is widely used as front-end for Functional Simulation, Formal Verification, hardware acceleration/emulation, low power applications, and mapping to specialized hardware architectures.
Key Features
Designed to meet the needs of EDA tool developers, Interra's suite of Standard Language Analyzers provide a memory optimal, robust, and easy-to-integrate front-end for standard languages and formats. Enabling EDA tool developers to concentrate on their core competency, rather than spending time writing parsers, these analyzers save resources and time to market high quality EDA products.